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Add support for [system]verilog

This commit is contained in:
Sameer Rahmani 2024-05-01 11:18:14 +01:00
parent a27f2bb795
commit 4b6ca4a90e
Signed by: lxsameer
GPG Key ID: 8741FACBF412FFA5
3 changed files with 125 additions and 0 deletions

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@ -34,6 +34,7 @@ let
./c-family
./python
./wm
./verilog
];
in
modules

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@ -0,0 +1,60 @@
# Fg42 - Emacs Editor for advance users
#
# Copyright (c) 2010-2024 Sameer Rahmani <lxsameer@gnu.org>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, version 2.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
# This is the home manager module that exposes FG42. It differs
# from FG42 modules that are structurally the same but used in
# different context
# A list of default FG42 modules to build FG42 with.
{ lib, config, pkgs, makeFG42Drv, ... }:
with lib;
let
cfg = config.fg42.verilog;
deps =
(with pkgs.emacsPackages; [
verilog-ext
verilog-mode
]);
drv = makeFG42Drv {
pname = "verilog";
version = config.fg42.version;
buildInputs = deps;
src = ./.;
};
in
{
options.fg42.verilog.enable = mkAndEnableOption "verilog";
config = mkIf cfg.enable {
fg42.elispPackages = [ drv ] ++ deps;
fg42.paths = (with pkgs;[
verible
verilator
]);
fg42.requires = [ drv.pname ];
meta = {
maintainers = [ maintainers.lxsameer ];
doc = ./README.md;
};
};
}

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@ -0,0 +1,64 @@
;;; FG42 --- The mighty editor for the emacsians -*- lexical-binding: t; -*-
;;
;; Copyright (c) 2010-2024 Sameer Rahmani & Contributors
;;
;; Author: Sameer Rahmani <lxsameer@gnu.org>
;; URL: https://devheroes.codes/FG42/FG42
;; Version: 4.0.0
;;
;; This program is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation, either version 3 of the License, or
;; (at your option) any later version.
;;
;; This program is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with this program. If not, see <http://www.gnu.org/licenses/>.
;;
;;; Commentary:
;;; Code:
(eval-when-compile
(require 'fpkg))
(use! verilog-mode
"Add support for verilog and system verilog to FG42. More info at
https://www.veripool.org/verilog-mode/")
(use! verilog-ext
"This package provides useful extensions on top of `verilog-mode' and `verilog-ts-mode'."
:hook (verilog-mode . verilog-ext-mode)
:init
(setq verilog-ext-eglot-default-server 've-svls)
(setq verilog-ext-feature-list
'(font-lock
xref
capf
hierarchy
eglot
lsp
flycheck
beautify
navigation
template
formatter
compilation
imenu
which-func
hideshow
typedefs
time-stamp
block-end-comments
ports))
:config
(setq verilog-ext-eglot-default-server 've-verible-ls)
;; I care more about ace-window than verilog-hs-toggle.
(define-key verilog-ext-mode-map (kbd "C-<tab>") #'ace-window)
(verilog-ext-eglot-set-server 've-verible-ls)
(verilog-ext-mode-setup))
(provide 'fg42/verilog)
;;; verilog.el ends here